Complementary metal oxide silicon8/31/2023 ![]() « lessĪccording to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. The experimental data indicate that the characteristics of the base region in MOS FETs are responsible for this anomalous change of 3-terminal electrical characteristics. Results of experiments to investigate the origin of the 'kink' effect (anomalous drain-current characteristics) of n-channel silicon-on-sapphire MOS field-effect transistors (FETs) were analyzed and related to hypothesized physical mechanisms. These studies concluded that the optimum-geometry approach is the preferred dose-rate radiation hardening method, since it does not involve the disadvantage inherent in the capactive inertia apporach (i.e., increased more » area, lower yield, lower reliability, higher dynamic power dissipation, and slower speed). Since sapphire photoconduction is the limiting transient radiation effect in SOS circuits, mathematical models for this phenomena were developed for the prediction of dose-rate failure thresholds for SOS integrated circuits. Measured circuit responses match those predicted by sapphire photoconduction theory within experimental accuracy. Responses of silicon-on-sapphire (SOS) circuits to transient radiation have been analyzed-based upon predicted and experimental results from individual transistors and Complementary-Symmetry/Metal Oxide Semiconductor (CMOS) digital SOS integrated circuits. Results of transient radiation measurements are reported which show the transient failure levels that can be expected in CMOS/SOS circuits and the significance of different threshold voltage combinations and sapphire photoresistive effects on the transient radiation hardness. These threshold voltages can result from exposure to ionizing radiation or instability in the gate insulator material. Results of electrical measurements are reported which show the variations that can be expected more » in electrical operation of these circuits, arising from the matrix of threshold voltage combinations. Simple CMOS/SOS test circuits, including an inverter, a 2-input NAND gate and a 2-input NOR gate, were fabricated with a 5 x 5-matrix of p-channel and n-channel threshold voltages. The Phase I study examined, experimentally, the effects of threshold voltage shifts on the electrical performance and transient radiation response in basic CMOS/SOS circuits. This report summarizes the results of Phase I of a three-phase program to develop and verify hardening techniques in Complementary-Symmetry/Metal Oxide Semiconductor (CMOS) Large Scale Integrated (LSI) circuits fabricated with Silicon-on-Sapphire (SOS) technology. ![]() At the time of publication, the circuit operation was verified but radiation data were not yet = , Folded cascode and three-stage operational amplifiers were fabricated on an SOI CMOS test chip supported by Texas Instruments, Incorporated. Several operational amplifier subcircuits are compared for their hardness characteristics. Radiation hardening topics discussed include superior radiation hardened topologies, photocurrent compensation and its limitations, and methods to ensure a preferred direction of photocurrent response. Analysis is performed on standard operational amplifier circuits and subcircuits to demonstrate the usefulness of these methods. Methods are presented for analysing circuit designs and minimizing the net photocurrent responses. Comparisons are made between each technology concerning photocurrent mechanisms and the inherent advantages of SOI CMOS. General strategies are developed for designing radiation hardened bulk and silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) operational amplifiers. ![]()
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